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www.fairchildsemi.com features fully integrated acquisition 3-channel video input multiplexer two-stage video clamp automatic gain adjustment sync detection and separation pixel and subpixel adjustment of hsync-to-video timing genlock to ntsc or pal inputs clock generation 8-bit video a/d converter microprocessor interface line-locked pixel rates - 12.27 mhz ntsc - 13.5 mhz ntsc or pal direct interface to tmc22x9x encoders built-in circuitry for crystal oscillator no tuning or external voltage reference required 68 lead plcc or 100 lead mqfp package applications frame grabber digital vcr/vtr desktop video description the tmc22071a genlocking video digitizer converts stan- dard baseband composite ntsc or pal video into 8-bit dig- ital composite video data. it extracts horizontal and vertical sync signals and generates a pixel clock for the on-board 8-bit a/d converter and a 2x clock for the transfer of data to subsequent video processing decoding or encoding with the tmc22x5y video decoder or tmc22x9x digital video encoder family. it also measures the color subcarrier phase and frequency and provides this data to the encoder (for gen- locked color ntsc or pal encoding), or a frame buffer (for frame capture) over the digital composite video port. the tmc22071a includes a three-channel video input mul- tiplexer, analog clamp, variable gain ampli?r, and digital back porch clamp. the on-board oscillator circuitry gener- ates the clock from a 20 mhz crystal or the clock source may be an external oscillator. it is programmable over a micro- processor interface for ntsc or pal operation. no external component changes and no production tuning or service adjustments are ever required. the tmc22071a is fabricated in an advanced cmos process, and is packaged in a 68 lead plcc or 100 lead mqfp. its performance is guaranteed from 0 c to 70 c. block diagram v in1 analog clamp gain d/a gvsync ghsync pxck 65-22071-01 ldv valid cvbs 7-0 back porch clamp data selector subcarrier phase-locked loop sync separator horizontal phase-locked loop direct digital synthesizer lowpass filter d/a +1.2v reset d 0 a 0 cs r/w int comp clk in clk out dds out pfd in pxck sel ext pxck c byp v ref r b r t control microprocessor interface analog interface dds/pixel clock interface mux v in2 v in3 a/d tmc22071a genlocking video digitizer rev. 1.0.5
tmc22071a product specification 2 functional description the tmc22071a is a fully-integrated genlocking video a/d converter which digitizes ntsc or pal baseband composite video under program control. it accepts video on three selectable input channels, adjusts gain, clamps to the back porch, and digitizes the video at a multiple of the horizontal line frequency. it extracts horizontal and vertical sync, mea- sures the subcarrier frequency and phase (relative to the sam- pling clock), and provides the data along with digital composite video data over an 8-bit digital video port. two sync outputs (ghsync and gvsync ) are also provided. it generates 1x (ldv) and 2x (pxck) pixel clocks for data transfer. pxck also serves as a master clock for the compan- ion tmc22x9x encoders and tmc22x5y decoders. operating parameters are set up via a serial microprocessor port. internal or external voltage reference operation is avail- able timing the tmc22071a operates from an internally-synthesized clock, pxck, which runs at twice the pixel data rate. the nominal pixel rates may be set to 12.27 mpps for ntsc and 13.5 mpps for ntsc and pal. customers requiring 14.75 or 15 mpps pal operation should consult factory. video input three high-impedance video inputs are selected by an inter- nal multiplexer under host processor control. the device accepts industry-standard video levels of 1.23 volts (sync tip to peak color = 1 volt sync tip to reference white). good channel-to-channel isolation allows active video on all three inputs simultaneously. antialiasing ?tering (if used) and line termination resistors must be provided externally. the input selection is controlled by two bits in the control regis- ter. analog clamp the front-end analog clamp ensures that the input video falls within the active range of the a/d converter. the digitized composite video output can be clamped to the back porch by a secondary digital clamp. automatic gain adjustment since video signals may vary substantially from nominal lev- els, the tmc22071a performs an automatic level setting routine to establish correct signal amplitudes for digitizing. the tmc22071a relies upon the presence of the sync tip-to-back porch voltage to determine the gain required for the input video signal. sync tip compression or clipping is often affected by apl (average picture level) variation. rather than tracking minor variations in sync tip amplitude and constantly adjust- ing video gain, the tmc22071a establishes proper signal amplitudes during initial genlock acquisition, and then (optionally) holds the gain constant. this results in a stable picture under variable signal conditions. improperly terminated or weak video signals are handled in the tmc22071a by a selectable gain of +1.0 or +1.5. the higher gain can amplify a doubly-terminated signal which is reduced in amplitude by 2/3. if the input signal levels are well controlled, the automatic gain adjustment can be disabled and the gain held at its nom- inal value (unity or 1.5x). analog-to-digital converter the tmc22071a contains a high-performance 8-bit a/d converter. its gain and offset are automatically set as a part of the automatic gain adjustment process during initial signal acquisition, and require no user attention. the reference voltages to the a/d converter are set up by internal d/a converters under automatic control during gen- lock acquisition. these voltages determine the gain and off- set of the a/d converter with respect to the video level presented at its input. low-pass filter the digitized composite video stream is digitally low-pass ?tered to remove chrominance components from the sync separator. filtering provides robust operation by optimizing the signal-to-noise ratio of the synchronizing/blanking por- tion of the video, improving the accuracy of the back porch blanking level detector. a digital sync separator provides the output sync signals, ghsync and gvsync , and times internal operations. horizontal phase-locked loop a phase-locked loop generates pxck, at twice the pixel rate. the reference signal for the horizontal phase-locked loop is generated by the direct digital synthesizer (dds). the dds output is constructed with an internal d/a con- verter and is output from the tmc22071a via the dds out pin. this signal is passed through an external lc ?ter and input to the horizontal phase-comparator. the frequency of the dds output is one ninth of that of pxck. a 20 mhz clock is required to drive the dds. preferably, this may be input to the tmc22071a via cmos levels on the clk in pin. alternately, a 20 mhz crystal may be directly connected between clk in and clk out with tuning capacitors to activate the internal crystal oscillator cir- cuitry. if incoming video is lost or disconnected after the tmc22071a has acquired and locked, pxck, ghsync ,
product specification tmc22071a 3 gvsync and grs data will continue. the grs data will be the initial subcarrier frequency and phase values selected by the format select bits of the control register. the tmc22071a will acquire and lock to incoming video within two frames after video is restored. subcarrier phase-locked loop a fully-digital phase-locked loop is used to extract the phase and frequency of the incoming color burst. these frequency and phase values are output over the cvbs bus during the horizontal sync period. fairchilds video decoder and gen- lockable encoder chips will accept these data directly. back porch digital clamp a digital back-porch clamp is employed to ensure a constant blanking level. it digitally offsets the data from the a/d con- verter to set the back porch level to precisely 3c h for ntsc and 40 h for pal. when the digital clamp is enabled, the cvbs video output data is determined from the a/d conver- sion result minus the back porch level + 3c h (40 h for pal). digitized video output the digitized 8-bit video output is provided over an 8-bit wide cvbs data port, synchronous with pxck and ldv. subcarrier frequency, subcarrier phase, and field id data (grs) are transmitted in 4-bit nibbles over cvbs 3-0 during the horizontal sync tip period at the pxck rate. microprocessor interface since microprocessor buses are notoriously noisy from a wide-band analog point of view, the microprocessor inter- face bus is only one bit wide, rather than the more customary eight. the operation of this bus is similar to other bus- controlled devices except that the tmc22071a internal control register is accessed one bit at a time. a sequence of 47 bits is written to or read from the lsb of a standard microprocessor port. writing to or reading from the secondary address results in the transfer of data to or from the internal shift register. the reset input, when low, sets all internal state machines to their initialized conditions. returning the reset pin high starts the signal acquisition sequence which lasts until locking with the gain-adjusted and clamped video signal is achieved. pin assignments 1 65-22071-02 68 v dd cvbs 0 cvbs 1 cvbs 2 cvbs 3 cvbs 4 v dd d gnd cvbs 5 cvbs 6 cvbs 7 ghsync gvsync valid d gnd d gnd ldv 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 v dd pxck d gnd d gnd v dd v dda a gnd v dda v dda a gnd r b v in3 v dda v in2 a gnd v dda v in1 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 pin name pin name a gnd r t a gnd v ref a gnd v dda a gnd c byp pfd in a gnd dds out pxck sel v dda comp a gnd d gnd clk in 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 v dd clk out ext pxck d gnd d gnd d gnd v dd v dd a 0 r/w cs v dd reset d gnd d 0 int d gnd 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 pin name pin name
tmc22071a product specification 4 pin assignments (continued) 65-22071-02b a 0 nc nc r/w cs v dd reset d gnd d 0 nc nc nc nc nc nc d gnd int v dd nc nc cvbs 0 cvbs 1 cvbs 2 cvbs 3 cvbs 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16* 17 18 19 20 21 22 23 24 25 130 31 50 51 80 100 81 v dd d gnd cvbs 5 cvbs 6 cvbs 7 nc ghsync gvsync valid nc nc nc d gnd d gnd ldv d gnd v dd nc v dd pxck d gnd d gnd v dd v dda a gnd 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41* 42* 43 44 45 46 47 48 49 50 pin name pin name v dda v dda nc nc a gnd nc r b v in3 nc v dda v in2 nc a gnd v dda v in1 nc a gnd r t a gnd v ref nc a gnd v dda a gnd c byp 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 nc pfd in nc nc nc a gnd dds out nc nc nc pxck sel v dda comp a gnd d gnd clk in v dd clk out ext pxck d gnd d gnd d gnd v dd nc v dd 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pin name pin name notes: 1. nc = do not connect. * these pins are not connected in the tmc22071a. however, you should connect these pins as shown for compatibility with future genlock ics. pin de?itions pin name pin number pin type function 68 pin plcc 100 pin mqfp video input v in1-3 34, 31, 29 65, 61, 58 1.23vp-p composite video input. video inputs,1.25 volts peak-to-peak, sync tip to peak color clocks clk in 51 91 cmos 20 mhz dds clock input. 20 mhz cmos clock input to dds. this pin may also be used along with clk out for directly connecting crystals. clk out 53 93 cmos inverted clock output. inverted dds clock output. this pin may also be used along with clk in for directly connecting a crystal. pxck 19 45 cmos 2x pixel clock output. 2x oversampled line-locked clock output. ldv 17 40 cmos pixel clock output. delayed pixel clock output. ldv runs at 1/2 the rate of pxck and its rising edge is useful for transferring cvbs digital video from the tmc22071a to the tmc22x9x digital video encoders. ext pxck 54 94 cmos external pxck input. input for external pxck clock source. pxck sel 46 86 cmos pxck source select. select input for internal or external pxck. when high, the internally generated line-locked pxck is selected. when low, the external pxck source is enabled.
tmc22071a product specification 5 digital video ghsync 12 32 cmos horizontal sync output. when the tmc22071a is locked to incoming video, the ghsync pin provides a negative-going pulse after the falling edge of the horizontal sync pulse. there is a fixed number of pxck clock cycles between adjacent falling edges of ghsync , except following a vcr headswitch. gvsync 13 33 cmos vertical sync output. when the tmc22071a is locked to incoming video, the gvsync pin provides a negative-going edge after the start of the first vertical sync pulse of a vertical blanking interval. cvbs 7-0 11-9, 6- 2 30-28, 25-21 cmos composite output bus. 8-bit composite video data is output on this bus at 1/2 the pxck rate. during horizontal sync, field id, subcarrier frequency, and subcarrier phase are available on this bus. m p l/o d 0 66 9 ttl data l/o port. microprocessor data port. all control parameters are loaded into and read back from the control register over this 1-bit bus. a 0 60 1 ttl m p port control. microprocessor address bus. a low on this input loads the l/o port shift register with data from d 0 and cs . a high transfers the l/o port shift register contents into the control register on the last falling edge of cs . cs 62 5 ttl chip select. when cs is high, d 0 is in a high-impedance state and ignored. when cs is low, the microprocessor can read or write d 0 data into the control register. reset 64 7 ttl master reset input. bringing reset low forces the internal state machines to their starting states, loads the control register with default values, and disables outputs. bringing reset high restarts the tmc22071a in its default mode. r/w 61 4 ttl bus read/write control. when r/w and a 0 are low, the microprocessor can write to the control register over d 0 . when r/w is high and a 0 is low, the contents of the status register are read over d 0 . int 67 17 ttl interrupt output. this output is low if the internal horizontal phase lock loop is unlocked with respect to incoming video for 128 or more lines per field. after lock is established, int goes high. valid 14 34 ttl hsync locked flag. this output, when high indicates that incoming horizontal sync has been detected within the 16 pixel window in time established by previous sync pulses. when low, it indicates that incoming horizontal sync has not been found within the expected time frame. valid will toggle if the time stability of incoming video is such that sync positioning varies more than 16 pixels or if occasional horizontal sync pulses are missing. pin de?itions (continued) pin name pin number pin type function 68 pin plcc 100 pin mqfp
product specification tmc22071a 6 analog interface v ref 38 70 +1.23 v v ref input/output. +1.23 volt reference. when the internal voltage reference is used, this pin should be decoupled to a gnd with a 0.1 m f capacitor. an external +1.2 volt reference may be connected here, overriding the internal reference source. comp 48 88 0.1 m f compensation capacitor. compensation for dds d/a converter circuitry. this pin should be decoupled to v dda with a 0.1 m f capacitor. r t ,r b 36, 28 68 0.1 m f a/d v ref decoupling. decoupling points for a/d converter voltage references. these pins should be decoupled to a gnd with a 0.1 m f capacitor. pll filter dds out 45 82 internal dds output. analog output from the internal direct digital synthesizer d/a converter, at 1/9 the pxck frequency. pfd in 43 77 horizontal pll input. analog input to the phase/frequency detector of the horizontal phase-locked loop. c byp 42 75 1 m f comparator bypass. decoupling point for the internal comparator reference of the phase/frequency detector. this pin should be decoupled to a gnd with a 0.1 m f capacitor. power supply v dda 23, 25, 26, 30, 33, 40, 47 49, 51, 52, 60, 64, 73, 87 +5 v analog power supply. positive power supply to analog section. v dd 1, 7,18, 22, 52, 58,59,63 6, 18, 26, 42, 44, 48, 92, 98, 100 +5 v digital power supply. positive power supply to digital section. ground a gnd 24, 27, 32, 35, 37, 39, 41, 44, 49, 50, 55, 63, 67, 69, 72, 74, 81, 89 0.0 v analog ground. ground for analog section. d gnd 8, 15, 16, 20, 21, 50, 55-57, 65, 68 8, 16, 27, 38, 39, 41, 46, 47, 90, 95- 97 0.0 v digital ground. ground for digital section. pin de?itions (continued) pin name pin number pin type function 68 pin plcc 100 pin mqfp
product specification tmc22071a 7 control and status registers the tmc22071a is controlled by a single 47-bit long con- trol register. access to the control register is via the i/o port shift register arranged as shown in figure 1. the con- trol register can be written, with the desired programming. the 12-bit status register is read-only and accessed through the same l/o port shift register. reading the status register yields information about blanking level, subcarrier presence, and whether or not pxck is locked or unlocked with respect to the line rate. figure 1. control and shift register structure the host processor writes data into the tmc22071a using only one bit of the microprocessors data and address bus. as shown in figure 2, the user should bring a 0 high for the cs falling edge preceding the introduction of bit 0 to the d 0 port. the next rising edge of cs completes the preloading of the control data, which transfer into the control register on the next rising edge of the pixel clock. the i/o port shift register, control register and status register are governed by cs , r/w , and a 0 . r/w and a 0 are latched by the tmc22071a on the falling edge of cs and data input d 0 is latched on the rising edge of cs . data read from d 0 is enabled by the falling edge of cs and disabled by the rising edge of cs . when the control register is read more than once consecutively, an extra cs pulse and accompanying a 0 is needed to align the circulated shift register data. i/o port shift register 65-22071-03 control register status register d 0 0464758 table 1. microprocessor port control the full sequence of 47 bits of control register data must be written each time a change in that data is desired. all or a few of the control and status register bits may be read, but the sequence always begins with bit 58 of the status register. figure 2. data write sequence figure 3. data read sequence a 0 r/w action 0 0 write data from d 0 into l/o port shift register 0 1 read d 0 data from last stage of l/o port shift register 1 0 transfer l/o port shift register contents to control register 1 1 enables continuous update of status bits in l/o port shift register cs r/w d 0 t h t s a 0 46 45 1 0 65-22071-04 cs r/w d 0 a 0 58 57 1 0 65-22071a-05
tmc22071a product specification 8 figure 4. control register map control register bit functions bit name function 0 sreset software reset. when low, resets and holds internal state machines, resets control register with previously written values, and disables output drivers. when high, sreset starts and runs state machines, pxck, and enables outputs. 1-3 format input signal format select. bit 3 is the msb. 000 ntsc at 12.27 mpps. 001 ntsc at 13.5 mpps. 010 reserved. 011 reserved. 100 pal at 13.5 mpps. 101 reserved. 11x reserved. 4-6 test factory test control bits. these should be set low. 7,8 source video source select. bit 8 is the msb. 00 v in1 01 v in2 1x v in3 9 vgain video gain. when low, gain is set to unity. when high, gain is set to 1.5x. 10-11 test factory test control bits. these should be set low. 12-16 subpix these control bits allows the hsync, vsync, and sample clock to be time-shifted by -16/32 to +15/32 pixels. bit 16 is the two? complement msb. when subpix is 00 h , hsync and incoming video are subject to leadlag. a value of 18 h delays hsync 1/4 pixel. a value of 08 h advances hsync 1/4 pixel. 17-24 leadlag this control word allows the hsync and vsync to be time-shifted -122 to +132 ldv cycles. when leadlag is 7b h , hsync and incoming video are in alignment. a value of 83 h delays hsync eight ldv cycles. a value of 73 h advances hsync eight ldv cycles. bit 24 is the msb. 0 00 000 00000 00 1 000 sreset leadlag agc freerun vcr/tv test bpfout dclamp cvbsen format test test test color lock test test (lsb) (msb) blkamp test test grsonly stval test subpix (lsb) leadlag source vgain 7 8 15 16 23 24 31 32 39 40 46 47 54 status register 65-22071-06 55 58
product specification tmc22071a 9 25 agc agc operation control. after h and v sync acquisition, the a/d converter references are adjusted to encompass the full video range. the system can initiate an a/d adjustment sequence at any time by bringing this bit high. the control bit will reset to 0 following agc adjustment. 26 frerun when high, a free-running pxck is generated, independent of incoming video. when low, pxck is locked to incoming video. 27-29 test factory test control bits. these should be set low. 30 vcr/tv block sync enable. when high the tmc22071a accepts both normal and block sync. (in block sync, the incoming signal is at the sync tip level for 2.5 (pal) or 3 (ntsc) consecutive lines. equalization pulses may be absent.) when low, only normal sync may be input. for most applications, whether using a vcr or a studio video input source, best performance will be found when this bit is high. 31 cvbsen cvbs bus enable. when low, the cvbs 7-0 , ghsync , and gvsync outputs are in a high-impedance state. when high, they are enabled. 32 test factory test control bit. this should be set low. 33 bpfout burst phase / frequency output control. when high, grs is disabled. when low, burst phase and frequency information is output on cvbs 3-0 . 34 dclamp digital clamp enable. the digital clamp is enabled when dclamp is high and disabled when low. 35-39 test factory test control bits. these should be set low. 40-43 stval sync tip value. when dclamp is high and stval is set to its default value 3 h the output sync level is 3 h for ntsc and 7 h for pal. bit 43 is the msb. 44 vcr vcr lock control. setting this bit low improves the tmc22071a? locking to vcr signals. when only clean video input signals are used, the user may set this bit high for compatibility with existing tmc22071 firmware. 45 test factory test control bit. this should be set low. 46 grsonly when the horizontal phase lock loop becomes unlocked (i.e. after video input is disconnected) and this control bit is high, all cvbs data is forced low except subcarrier frequency and phase data (grs). ghsync , gvsync , and pxck continue with default grs data until video is required. the presence of grs also depends upon bit 33. if the grsonly bit is low, ghsync , gvsync , and pxck continue with default grs data continue but video pixel data is random. status bits (read only) 47 color burst present status bit. this bit is high when burst is present on the input video. it is low, when burst is not present. 48-55 blkamp blanking amplitude status bit. these eight bits report the actual blanking level. 56 lock h-lock loop status bit. when high, the tmc22071a is not locked to an input signal. when low, lock has been achieved. 57-58 test these are read-only bits for testing puposes only. control register bit functions (continued) bit name function
tmc22071a product specification 10 horizontal timing horizontal line rate is selectable, and is determined by the format control bits (12.27 mpps for ntsc, 13.5 mpps for ntsc and pal). figure 5 illustrates the horizontal blanking interval. figure 6 completes the de?ition of timing parameters with vertical blanking interval detail. figure 5. horizontal sync timing figure 6. vertical sync timing programming the tmc22071a upon power-up after bringing reset low, the tmc22071a control register is set to default values as shown in the top entry of table 3. these default values do not necessarily render the tmc22071a operational in any speci? application. before the tmc22071a is expected to acquire input video, its control register must be loaded with data that is speci? to its use. 65-22071-07 video in burst ghsync t dh h 2.35 sec pal 2.3 sec ntsc equalizing pulse t dh t vd 0.5h 4.7 sec serration video in 65-22071-08 gvsync ghsync (odd field) ghsync (even field) table 2.tmc22071a timing options table 3. control register example data standard field rate (hz) line rate (khz) pixel rate (mpps) pxck frequency (mhz) plxels per line ntsc 59.94 15.734264 12.2727+ 24.54+ 780 ntsc-601 59.94 15.734264 13.50 27.0 858 pal-601 50.00 15.625 13.50 27.0 864 standard control register data (bit 56 bit 0) 46 42 38 34 30 26 22 18 14 10 6 2 default 0000 0110 0000 1001 0000 0010 0000 0000 0000 0000 0000 001 ntsc 0010 0110 0000 1001 1000 0010 0000 0000 0000 00xx 0000 000 ntsc-601 0010 0110 0000 1001 1000 0010 0000 0000 0000 00xx 0000 010 pal-601 0010 1110 0000 1001 1000 0010 0000 0000 0000 00xx 0001 xx0
product specification tmc22071a 11 cvbs bus data formats the cvbs bus outputs a genlock reference signal (grs) along with the 8-bit digital composite video data. the range of output data versus video input voltage is illustrated in figure 7 where sync tip and blanking levels are controlled by the digital backporch clamp of the tmc22071a. during horizontal sync, the tmc22071a outputs ?ld identi?a- tion, subcarrier frequency, and subcarrier phase information on the cvbs bus. figure 7. output data vs. input video level peak chrominance peak luminance back porch burst 65-22071-0 9 blanking sync tip ntsc pal fe h ff h d2 h cf h 3c h 40 h 03 h 03 h field identi?ation is output on cvbs 2-0 . the lsb, cvbs 0 , will be low during odd ?lds and high for even ?lds. when ntsc operation is selected, cvbs 1-0 count 00,01,10,11 for ?lds 1 through 4 respectively. when pal operation is selected, cvbs 2-0 count 000, 001, 010, etc. to 111 for ?lds 1 through 8, respectively. cvbs 3 indicates v-component inversion in pal. it is high for ntsc lines (burst 135 ) and low for pal lines (burst 225 ) subcarrier frequency is sent out in a 24-bit binary represen- tation in six 4-bit nibbles on cvbs 3-0 . subcarrier frequency data, f 23-0 , is identical to the pre-programmed bseed value used in the tmc22071a to lock the subcarrier phase-locked loop to the incoming subcarrier frequency. subcarrier phase, f 23-0 , is also sent out in a 24-bit binary representation in six 4-bit nibbles on cvbs 3-0 . bit f 23 is the msb. figure 8. genlock reference signal (grs) format figure 9. cvbs bus video data format pxck 01 pixel pixel pixel field identification frequency phase pixel pixel 65-22071-10 f 23:20 f 19:16 f 15:12 f 11:8 f 7:4 f 3:0 f 23:20 f 19:16 f 15:12 f 11:8 f 7:4 f 3:0 2 3 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 ghsync cvbs 7:0 pxck 65-22071-11 pixel 0 pixel 1 ldv cvbs 7:0 t ho t xl t do t xv t pwhpx t pwhpx 1/f pxck ghsync
tmc22071a product specification 12 figure 10. microprocessor port ?write timing figure 11. microprocessor port ?read timing t pwlcs t ha t sa cs r/w a 0 65-22071-12 d 0 t hd t sd t pwhcs t pwlcs t ha t sa cs r/w a 0 65-22071-13 d 0 t hom t dom t doz t pwhcs
product specification tmc22071a 13 equivalent circuits and transition levels figure 12. equivalent pfd in circuit figure 13. equivalent dds out circuit figure 14. equivalent digital input circuit figure 15. equivalent digital output circuit figure 16. transition levels for three-state measurements v dd v dd n substrate 65-22071-14 2k ? pp pfd in c byp +2.4 v + e v dd v dd dds out 65-22071-15 150 ? np n substrate p n input 65-22071-16 v dd v dd output 65-22071-17 p n cs t dom t doz t hom 0.5 v 65-22071-18 0.5 v 2.0 v 0.8 v hi-z d 0
tmc22071a product specification 14 absolute maximum ratings (beyond which the device may be damaged) 1 notes: 1. absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. functional operation under any of these conditions is not implied. 2. applied voltage must be current limited to specified range, and measured with respect to gnd. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current, flowing into the device. operating conditions (for standard temperature range) note: 1. timing reference points are at the 50% level. parameter min. max. unit. power supply voltage -0.5 7.0 v input voltage -0.5 v dd + 0.5 v digital outputs applied voltage 2 -0.5 v dd + 0.5 v forced current 3,4 -6.0 6.0 ma short circuit duration (single output in high state to gnd) 1 sec temperature operating, case -60 130 c operating, junction 150 c lead soldering (10 seconds) 300 c vapor phase soldering (1 minute) 220 c storage -65 150 c parameter min. nom. max. units v dd power supply voltage 4.75 5.0 5.25 v v ih input voltage, logic high ttl inputs 2.0 v dd v cmos inputs 2/3v dd v dd v v il input voltage, logic low ttl inputs d gnd 0.8 v cmos inputs d gnd 1/3 v dd v i oh output current, logic high -2.0 ma l ol output current, logic low 4.0 ma v in video input signal level, sync tip to peak white 1.0 v v ref external reference voltage 1.235 v t a ambient temperature, still air 0 70 c microprocessor interface t pwhcs cs pulse width, low 50 ns t pwhcs cs pulse width, high 50 ns t sa address setup time 0 ns t ha address hold time 16 ns t sd data setup time 20 ns t hd data hold time 0 ns
product specification tmc22071a 15 electrical characteristics (for standard temperature range) note: 1. typical i dd with v dd = +5.0 volts and t a = 25 c, maximum i dd with v dd = +5.25 volts and t a = 0 c. switching characteristics (for standard temperature range) parameter conditions min typ max units i dd power supply current 1 total current v dd = max, f pxck = 30mhz 190 230 ma i ref reference inputcurrent v ref = +1.235v 100 m a i ih input current, logic high v dd = max, v in = 4.0v 10 m a i il input current, logic low v dd = max, v in = 0.4v 10 m a v oh output voltage, logic high i oh = -2.0 ma 2.4 v v ol output voltage, logic low i ol = 4.0 ma 0.4 v i ozh hi-z output leakage current, high v dd = max, v in = v dd 10 m a i ozl hi-z output leakage current, low v dd = max, v in =gnd 10 m a c l digital input capacitance t a = 25 c, f = 1 mhz 4 15 pf c o digital output capacitance t a - 25 c, f = 1 mhz 10 pf c v input capacitance, v in1-3 t a = 25 c, f = 3.58 mhz 15 pf r v input resistance, v in1-3 50 k w parameter conditlons min typ max units t do output delay time c load = 35 pf 2 15 ns t ho output hold time 3 8 ns f pck pixel rate 12 15.3 mhz f pxck master clock rate 24 30.6 mhz t pwhpx pxck pulse width, low 12 ns t pwhpx pxck pulse width, high 12 ns t dh horizontal sync to ghsync 14 pixels t vd vertical sync to gvsync 14 pixels t xl pxck low to ldv high 8 ns t xv pxck low to ldv low 8 ns t dom d 0 enable time 20 ns t hom d 0 disable time 10 15 ns t doz cs low to d 0 output driven 5 ns
tmc22071a product specification 16 system performance characterlstics note: 1. ntsc/pal compliant black burst at nominal input level 10%, frequencies nominal 10 ppm. figure 17. typical interface circuit parameter min type max units e sch sync time-base variation 1 3ns e scp subcarrier phase error 1 2 degrees t al line-lock acquisition time 2 frames v xt channel-to-channel crosstalk @3.58 mhz -35 db 10 f +5v digital supply plane analog supply plane* ferrite bead +5v 75 ? v in1 v ref r t r b cvbs 7:0 c byp ghsync d gnd dds out microprocessor interface tmc22071a genlocking video digitizer digital video interface pfd in comp v dd v dda a gnd v in2 v in3 ext pxck clk in int valid reset d 0 a 0 cs r/w clk out pxck sel video a video b video c 20 mhz, ttl and must be connected via low-impedance path *section of supply plane beneath analog interface circuitry 75 ? 75 ? 3.3 f 3.3 f 3.3 f lpf lpf lpf 10 f 6.8 pf 10 h 150 pf 390 pf 0.01 f 0.1 f 0.1 f 0.1 f lm385-1.2 0.1 f 8 0.1 f 0.1 f 0.1 f 3.3k ? gvsync pxck ldv 65-22071a-19 application notes the tmc22071a is a complex mixed-signal vlsi circuit. it produces cmos digital signals at clock rates of up to 15 mhz while processing analog video inputs with a resolu- tion of less than a few millivolts. to maximize performance it is important to provide an electrically quiet operating environment. the circuit shown in figure 17 provides an optional external 1.2v reference to the v ref input of the tmc22071a. the internal v ref source is adequate for most applications. flltering inexpensive low-pass anti-aliasing ?ters are shown in fig- ures 18 and 20. these ?ters would normally be inserted in the video signal path just before the 75 w terminating resis- tor and ac-coupling capacitor for each of the three video inputs, v in1-3 . the ?ter of figure 18 exhibits a 5th-order chebyshev response with-3db bandwidth of 6.7mhz and a group delay of 140 nanoseconds at 5mhz. the ?ter of figure 19 has been equalized for group delay in the video signal band. its -3db passband is 5.5mhz while the group delay is constant at 220 nanoseconds through the dc to 5mhz frequency band. figure 18. simple anti-aliasing filter 2.2 h 470 pf 65-22071-20 470 pf 1000 pf 2.2 h
product specification tmc22071a 17 figure 19. group delay equalizer filter using a 20 mhz crystal in systems where a 20 mhz clock is not available, a crystal may be used to generate the clock to the tmc22071a. the crystal must be a 20 mhz ?undamental?type, not overtone. speci? crystal characteristics are listed in table 4 and the connections are shown in figure 20. table 4. crystal parameters figure 20. direct crystal connections parameter value fundamental frequency 20 mhz tolerance 30 ppm @ 25 c stability 50 ppm, 0 c to 70 c load capacitance 20 pf shunt capacitance 7 pf max. esr 50 w , max. 3.3 h 3.3 h 4.7 h 2.2 h 910 h 4.7 h 430 pf 65-22071-21 750 pf 430 pf 470 pf 470 pf 33 pf 20 mhz crystal 65-22071a-22 clk in tmc22071a 300 ? 1m ? clk out 33 pf grounding the tmc22071a has separate analog and digital circuits. to minimize digital crosstalk into the analog signals, the power supplies and ground connections are provided over separate pins (v dd and v dda are digital and analog power supply pins; d gnd and a gnd are digital and analog ground pins). in general, the best results are obtained by tying all grounds to a solid, low-impedance ground plane. power supply pins should be individually decoupled at the pin. power supply noise isolation should be provided between analog and digi- tal supplies via a ferrite bead inductor on the analog lead. ultimately all +5 volt power to the tmc22071a should come from the same power source. another approach calls for separating analog and digital ground. while some systems may bene? from this strategy, analog and digital grounds must be kept within 0.1v of each other at all times. interface to the tmc22x9x encoder the tmc22x9x digital video encoders have been designed to directly interface to the tmc22071a digital video genlock. the tmc22071a is the source for tmc22x9x input signals cvbs 7-0 , ghsync , gvsync , ldv, and pxck as shown in figure 21. these signals directly connect to the tmc22x9x. the microprocessor interface for tmc22x9x and tmc22071a are identical. all r/w , reset , data and address bus signals from the host micro- processor are shared by the tmc22x9x and tmc22071a. only cs , valid, and int signals are separate from the microprocessor bus. figure 21. tmc22x9x interface circuit cvbs 7:0 ghsync gvsync reset d 0 a 0 cs r/w pxck ldv 65-22071a-23 tmc22071a genlocking video digitizer tmc22x9x digital video encoder microprocessor interface 8 8 2 cvbs 7:0 ghsync gvsync pxck ldv reset d 7:0 a 1:0 cs r/w
tmc22071a product specification 18 printed circuit board layout designing with high-performance mixed-signal circuits demands printed circuits with ground planes. wire-wrap is not an option. overall system performance is strongly in?- enced by the board layout. capacitive coupling from digital to analog circuits may result in poor picture quality. con- sider the following suggestions when doing the layout: 1. keep the critical analog traces (comp,v ref , r t , r b , dds out, pfd in, c byp , and v in1-3 ) as short as pos- sible and as far as possible from all digital signals. the tmc22071a should be located near the board edge, close to the analog output connectors. 2. the digital power plane for the tmc22071a should be that which supplies the rest of the digital circuitry. a sin- gle power plane should be used for all of the v dd pins. if the analog power supply for the tmc22071a is the same as that of the systems digital circuitry, power to the tmc22071a v dda pins should be decoupled with ferrite beads and 0.1 m f capacitors to reduce noise. 3. the ground plane should be solid, nor cross-hatched. connections to the ground plane should have very short leads. 4. decoupling capacitors should be applied liberally to v dd pins. remember that not all power supply pins are created equal. they typically supply adjacent circuits on the device, which generate varying amounts of noise. for best results, use 0.1 m f capacitors in parallel with 10 m f capacitors. lead lengths should be minimized. ceramic chip capacitors are the best choice. 5. if the digital power supply has a dedicated power plane layer, it should not overlap the tmc22071a, the voltage reference or the analog outputs. capacitive coupling of digital power supply noise from this layer to the tmc22071a and its related analog circuitry can degrade performance. 6. clk should be handled carefully. jitter and noise on this clock or its ground reference may degrade perfor- mance. terminate the clock line carefully to eliminate overshoot and ringing. related products tmc22x9x digital video encoders tmc2242/tmc2243/tmc2246 video filters tmc2081 digital video mixer tmc22x5y digital decoders tmc2302 image manipulation sequencer
product specification tmc22071a 19 notes:
tmc22071a product specification 20 notes:
product specification tmc22071a 21 notes:
tmc22071a product specification 22 mechanical dimensions 68 lead plcc package -c- b lead coplanarity ccc c d d1 e1 e j a d3/e3 e j b1 a1 a2 a .165 .200 4.19 5.08 symbol inches min. max. min. max. millimeters notes a1 .090 .130 2.29 3.30 a2 .020 .51 b .013 .021 .33 .53 d/e .985 .995 25.02 25.27 d1/e1 .950 .958 24.13 24.33 d3/e3 .800 bsc 20.32 bsc .050 bsc 1.27 bsc e j .042 .056 1.07 1.42 2 3 nd/ne 17 17 68 68 n ccc .004 0.10 b1 .026 .032 .66 .81 notes: 1. 2. 3. all dimensions and tolerances conform to ansi y14.5m-1982 corner and edge chamfer (j) = 45 ? dimension d1 and e1 do not include mold protrusion. allowable protrusion is .101" (.25mm)
product specification tmc22071a 23 mechanical dimensions (continued) 100 lead mqfp package ?3.2mm footprint lead detail a1 aa2 b -c- lead coplanarity seating plane ccc c see lead detail e e1 d1 d b pin 1 indentifier e base plane r c l a datum plane 0 ? min. .20 (.008) min. .13 (.30) .005 (.012) .13 (.005) r min. 0.076" (1.95mm) ref a ? .134 ? 3.40 symbol inches min. max. min. max. millimeters notes a1 .010 ? .25 ? .015 .38 a2 .100 .120 2.55 3.05 b .008 3, 5 5 .22 .009 .23 c .005 .13 e .667 .687 16.95 17.45 .0256 bsc .65 bsc e l .028 .040 .73 1.03 100 100 30 30 4 n nd 20 20 ne a 0 ? 7 ? 0 ? 7 ? ? .004 ? .12 ccc d .904 .923 22.95 23.45 d1 .783 .791 19.90 20.10 e1 .547 .555 13.90 14.10 notes: 1. 2. 3. 4. 5. all dimensions and tolerances conform to ansi y14.5m-1982. controlling dimension is millimeters. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "b" dimension. dambar cannot be located on the lower radius or the foot. "l" is the length of terminal for soldering to a substrate. "b" & "c" includes lead finish thickness.
tmc22071a product specification 7/24/98 0.0m 002 stock#ds7022071a 1998 fairchild semiconductor corporation life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ordering information note: 1. 100 lead mqfp is strongly recommended for all new board designs. product number temperature range screening package package marking TMC22071AR1C t a = 0 c to 70 c commercial 68-lead plcc 22071ar1c tmc22071akhc 1 t a = 0 c to 70 c commercial 100-lead mqfp 22071akhc

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